`timescale 1ns/1ps
module mux2_tb();

	reg S0;// 随时需要修改数值的变量用reg类型
	reg S1;
	reg S2;
	
	wire mux2_out;// 导线 便于仿真监视信号	
	
mux2 mux2(
	.a(S0),
	.b(S1),
	.sel(S2),
	.out(mux2_out)
);

	initial begin
		S2 = 0; S1 = 0; S0 = 0;
		#20;
		S2 = 0; S1 = 0; S0 = 1;
		#20;
		S2 = 0; S1 = 1; S0 = 0;
		#20;
		S2 = 0; S1 = 1; S0 = 1;
		#20;
		S2 = 1; S1 = 0; S0 = 0;
		#20;
		S2 = 1; S1 = 0; S0 = 1;
		#20;
		S2 = 1; S1 = 1; S0 = 0;
		#20;
		S2 = 1; S1 = 1; S0 = 1;
		#20;
	end

endmodule
